Programmable signal generator

Práce pojednává o návrhu a realizaci hardwaru programovatelného generátoru analogových a digitálních signálů pomocí mikrokontroléru. Je zde popsána funkce navrhovaného generátoru, výběr použitých součástek a jejich zapojení, např. návrh obvodů pro převod digitálního signálu na analogový a jeho následnou úpravu (zesílení a nastavení offsetu). Dále je zde popsán komunikační protokol pro připojení generátoru k PC pomocí USB třídy HID, vývoj aplikace pro ovládání generátoru a firmwaru řídícího mikrokontroléru. Na závěr jsou uvedeny výsledky měření, srovnání měřených a simulovaných charakteristik.This thesis treats designing and the implementation of the Programmable Signal Generator which generates analog and digital signals using microcontroller. It describes the function of the generator, component selection and their implementation into the circuit, for example design of circuits for digital to analog conversion and the final adjustment of generated analog signals (amplification and offset setting). It also describes the communication protocol between the generator and personal computer using USB HID class, the development of graphical user interface and microcontroller firmware. Lastly, the measurement results are presented and compared with simulation results.

Development of an FPGA-based gate signal generator for a multilevel inverter

The application of Field Programmable Gate Array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density. This paper presents an FPGA-based gate signal generator for a multilevel inverter employing an online optimal PWM switching strategy to control its output voltage. FPGA is chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can ensure the accuracy of the instants that gating signals are generated. The gate signal generator has been realized by an FPGA (FLEXlOKZO) from Altera. The design and development of the FPGA based gate signal generator is described in detail. Results from the timing simulation using MAX+PLUSII software are given and verified by the results obtained from the FLEXlOK2O output

Natural simulation of the generator of sinusoidal signals on NI Digital Electronics Board

The article touches on the actual problem of transmitting data of a given form and frequency to the air using programmable logic integrated circuits. Field Programmable Gate Array. The goal of the article is the implementation of a sinusoidal signal generator on a FPGA. The developed device will be used to transmit an analog program-controlled signal of a given shape and frequency to the air. The signal parameters will be controlled on the PC via the FPGA

Hardware Design for Quadrature Phase Detection Algorithm in ECVT

Core processing for calculating phase andamplitude of the detected signal was built on FPGA (Field-Programmable Gate-Array) platform. Phase shift demodulationalgorithm employs IP core provided by Xilinx FPGA. Directdigital synthesizer (DDS), multiplier, accumulator, and CORDIC(coordinate rotation digital computer) modules were used asexcitation-reference signal generator, signal multiplication,accumulation, and conversion to polar coordinate in order toconduct trigonometric operation respectively. Hardware designwas emulated on MATLAB-Xilinx System Generator to observeits performance. Phase detection range 0-114.58o and meanabsolute error 0.58o have been achieved. Data processing ratesolely at digital signal stage was approximately 100data/s suitablefor 32-channel ECVT (electrical capacitance volumetomography) system

A self-calibration circuit for a neural spike recording channel

This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2 , with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Implementation of a software defined radio on FPGAs using system generator

The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board. The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board

REFERENCE SIGNAL GENERATOR OF DOPPLER MODULATOR DRIVER OF MÖSSBAUER SPECTROMETER

This research work is devoted to the development of reference signal generator of Mössbauer spectrometer. This generator forms signal of special form thus providing necessary lowering of motion of Doppler modulator with low error value. As reference signal generator, a programmable function generator on the base of an AT90S8515 microcontroller and a 12-bit digital-to-analog converter were used

ACE 16k based stand-alone system for real-time pre-processing tasks

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128×128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.European Commission IST2001 – 38097Ministerio de Ciencia y Tecnología TIC2003 – 09817- C02 – 01Office of Naval Research (USA) N00014021088